%FILENAME%
vtr-9.0.0-1.0-i686.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1.0

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
6982771

%ISIZE%
25420836

%MD5SUM%
777c52ca2253e4663f1fe6b6749301ba

%SHA256SUM%
e395e85b5b58eafc7fb7f62731dcd27f7b1f3c917c2a179243397b9e61fe881c

%PGPSIG%
iQEzBAABCgAdFiEEFhlKgiMenvgjViGByOj1oK+bp+cFAmiyNccACgkQyOj1oK+bp+cHxQf/b5mvIa14IDfncxSOKUuKjt9Kj4W9SFqP990cOAUir5eQcQDEvleIUaGVOvQj4uq8FPko5FJ3eiC96HQxc1eu+9uKaLObHoqrd8LSdToe71xy8aDijW2d96fqm3OxVjsZBh7DUKmE+WpZPdBX/vhEHWIKiwB+ztaT8U/22c8Jm/3FJx7f8XSLWWgDvpk02VvussmzEs8Og2jLlMwOusVW/aZ8NwjrmM2JBFKep4YmIuqdbovCdXM8NC6VgEtr2RFINdSYOk2YIr31oafcDWcv3CRxJDkB4Da1UfQPRvy7YCbFInQr4zpxkugiV4+qqPSJYmW9V8K4rpTF5X3wujsJKQ==

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
i686

%BUILDDATE%
1756507991

%PACKAGER%
Andreas Baumann <mail@andreasbaumann.cc>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

